1. Field of the Invention
The present invention relates generally to a semiconductor structure and, more particularly, to an improved memory structure having low-resistance buried digit lines and method of forming the same.
2. Description of the Prior Art
Electronic storage devices such as dynamic random access memory (DRAM) have been an essential resource for the retention of data. Conventional semiconductor DRAM typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor memory often requires densely packed capacitor structures that are easily accessible for electrical interconnection.
The capacitor and transistor structures are generally known as memory cells. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a digit line, one of which addresses a “column” of memory cells while the other addresses a “row” of memory cells. Recently, there has been increasing research on the buried word line/digit line cell array transistor in which a word line or a digit (bit) line is buried in a semiconductor substrate below the top surface of the substrate.
However, as the packing density in integrated circuits increases, it becomes more difficult to reduce the resistance of a buried digit line in the memory array. Therefore, there is a need in this industry to provide an improved memory structure and fabrication method thereof in order to cope with such problems.